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 EMIF02-USB02F2
2-line IPADTM, EMI filter with ESD protection
Features

2-line low-pass filter + ESD protection High efficiency in EMI filtering Lead-free package Very low PCB space occupation < 3.2 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Figure 1. Pin layout (bump side)
4 3
VCC
Flip Chip (10 bumps)
2
1
I6
A B
Complies with the following standards:
I4 O2 I3 O1
I5 I2 GND I1
IEC 61000-4-2 - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3 Figure 2.
I6 I5 I4 D1
C D E
Application
EMI filtering and ESD protection for USB port.
Basic cell configuration
VCC R3 1.3k R2 33
I2 O2
Description
The EMIF02-USB02F2 is a highly integrated array designed to suppress EMI / RFI noise for a USB port. The EMIF02-USB02F2 Flip Chip packaging means the package size is equal to the die size. Additionally, this filter includes ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV.
R4 10k I3
25pF 25pF GND 25pF 25pF R1 33 I1 O1
GND
April 2008
Rev 2
1/7
www.st.com 7
Characteristics
EMIF02-USB02F2
1
Characteristics
Table 1.
Symbol VPP Tj Top Tstg
Absolute ratings (Tamb = 25 C)
Parameter and test conditions ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge Junction temperature Operating temperature range Storage temperature range Value 15 8 125 - 40 to + 85 - 55 to + 150 Unit kV C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM Cline R1,R2 R3 R4 VF
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between input and output Input capacitance per line Test conditions IR = 1 mA VRM = 3V @ 0V Tolerance 5% Tolerance 5% Tolerance 5% @ 1 mA (D1 diode) 33 1.3 10 1 Min. 6 0.1 0.5 50 Typ. Max. Unit V A pF k k V
IPP VCL VBR VRM IR IRM IRM IR VRM VBR VCL V I IPP
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EMIF02-USB02F2
Characteristics
Figure 3.
0.00 dB - 5.00 - 10.00 - 15.00
Attenuation measurement
Figure 4.
0.00
dB
Analog crosstalk measurement (I1- O2)
- 10.00 - 20.00 - 30.00
- 20.00
- 40.00
- 25.00 - 30.00 - 35.00 - 40.00 - 45.00 - 50.00 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G
- 50.00 - 60.00 - 70.00 - 80.00 - 90.00 100.0k
1.0M
10.0M
f/Hz
100.0M
1.0G
Figure 5.
ESD response to IEC 61000-4-2 (+15kV contact discharge)
Figure 6.
Line capacitance versus reverse applied voltage
C(pF)
40 35 30 25 20 15
VR(V)
10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
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Application information
EMIF02-USB02F2
2
Application information
Figure 7. Aplac model of D+ & D- cells
C1 650 650 A3
0.8pF
+
+
Csub rsub_1k3
+
Csub rsub_1k3
+
Csub
+ 0.8pF
D2
bulk
C1 or E1
16.5
16.5
C3 or E3
50pH Cbump I/O
0.8pF MODEL = D02_usb
+
+
Csub rsub_33R
+
Csub rsub_33R
+
Csub
+ 0.8pF
MODEL = D02_usb
+
Rbump bulk 50m
100m D2
MODEL = D02_usb MODEL = D02_5p MODEL = D02_5p MODEL = D02_usb
bulk Lhole
Rsub_D
Rsub_D
100m
D2 bulk
D2
Figure 8.
Aplac model parameters
Cz 17pF opt Ls 0.4nH Rs 0.1 Rsub_D 10 Csub 0.3pF Rsub_33R 16 Rsub_1k3 18 lhole 170pH opt Cbump 1.2pF opt Rbump 350 D02_usb diodes model + BV = 7 + IBV = 1m + CJO = Cz + M = 0.3333 + RS = 2 + VJ = 0.6 + TT = 100n D02_5p diodes model + BV = 100 + IBV = 1m + CJO = 5p + M = 0.3333 + RS = 2 + VJ = 0.6 + TT = 100n
3
Ordering information scheme
Figure 9. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x 2: Lead free, pitch = 500 m, bump = 315 m
yy
-
xxx zz
Fx
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EMIF02-USB02F2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 10. Flip Chip package dimensions
700m 50 315m 50 650m 65
495m 50
495m 50
285 m 1.62mm 50m
Figure 11. Footprint recommendations
Copper pad Diameter: 250 m recommended, 300 m max. Solder stencil opening: 330 m recommended
Figure 12. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
285 m
1.97mm 50m
E
Solder mask opening recommendation: 340 m min. for 300 m copper pad diameter
xxz y ww
5/7
Ordering Information Figure 13. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
EMIF02-USB02F2
1.75 0.1 3.5 0.1
2.07
0.73 0.05
All dimensions in mm
8 0.3
STE
STE
STE
xxz yww
User direction of unreeling
xxz yww
xxz yww
4 0.1
1.72
Note:
More information is available in the application notes: AN1235: "Flip Chip: Package description and recommendations for use" AN1751: "EMI Filters: Recommendations and measurements"
5
Ordering Information
Table 3. Ordering information
Marking FG Package Flip Chip Weight 4.25 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF02-USB02F2
6
Revision history
Table 4.
Date
14-Dec-2004
Document revision history
Revision
1
Changes First issue Updated ECOPACK statement. Updated Figure 9, Figure 10, Figure 12, and Figure 13. Reformatted to current standards.
28-Apr-2008
2
6/7
EMIF02-USB02F2
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